Researchers from Tohoku University, University of Messina, and University of California, Santa Barbara (UCSB) have developed a large-scale version of a probabilistic computer (p-computer) with stochastic spintronic devices that suitable for difficult computational problems like combinatorial optimization and machine learning.
Moore’s Law predicts that computers become faster every two years due to the evolution of semiconductor chips. Although this has happened historically, continued evolution is beginning to lag behind. Machine learning and artificial intelligence revolutions require much higher computational capacity. Quantum computing is one way to address these challenges, but significant hurdles to the practical realization of scalable quantum computers remain.
A p-computer operates naturally stochastic building blocks called probabilistic bits (p-bits). Unlike traditional computer bits, p-bits oscillate between states. A p-computer can operate at room temperature and acts as a domain-specific computer for a wide variety of applications in machine learning and artificial intelligence. Just as quantum computers attempt to solve intrinsically quantum problems in quantum chemistry, p-computers attempt to tackle probabilistic algorithms, widely used for complex computational problems in combinatorial optimization and sampling.
Recently, researchers from Tohoku University, Purdue University, and UCSB have shown that p-bits can be achieved efficiently using appropriately modified spintronic devices called stochastic magnetic tunnel junctions (sMTJs). . So far, sMTJ-based p-bits have been implemented on a small scale; and only the proofs of concept of the spintronic p-computer for combinatorial optimization and machine learning have been demonstrated.
The research group presented two important breakthroughs at the 68th International Electronic Devices Meeting (IEDM) on December 6, 2022.
First, they showed how sMTJ-based p-bits can be combined with conventional and programmable semiconductor chips, namely Field-Programmable-Gate-Arrays (FPGAs). The “sMTJ + FPGA” combination allows much larger p-bit arrays to be implemented in hardware, going beyond previous small-scale demonstrations.
Second, probabilistic emulation of a quantum algorithm, Simulated Quantum Annealing (SQA), has been performed in heterogeneous p-computers “sMTJ+FPGA” with systematic evaluations for difficult combinatorial optimization problems.
The researchers also compared the performance of sMTJ-based p-computers to that of conventional computer hardware, such as graphics processing units (GPUs) and tensor processing units (TPUs). They showed that p-computers, using a high-performance sMTJ previously demonstrated by a team at Tohoku University, can achieve massive improvements in throughput and power consumption over conventional technologies.
“Currently, the p’s-MTJ+FPGA computer is a prototype with discrete components,” said Professor Shunsuke Fukami, who was part of the research group. “In the future, embedded p-computers using magnetoresistive random-access memory (MRAM) technologies compatible with semiconductor processes might be possible, but this will require a co-design approach, with experts in materials, physics, design of circuits and algorithms that must be brought into play.”
Experimental evaluation of simulated quantum annealing with MTJ-augmented p-bits. IEEE 68th International Annual Meeting on Electronic Devices
Provided by Tohoku University
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